Shrike ExamplesΒΆ
π’ Beginner Β Β π‘ Intermediate Β Β π΄ Advanced
# |
Example |
Folder Name |
Category |
Difficulty |
Why |
|---|---|---|---|---|---|
1 |
|
Getting Started |
π’ Beginner |
Single output signal, no state |
|
2 |
|
Getting Started |
π’ Beginner |
Simple PWM counter, single module |
|
3 |
|
Getting Started |
π’ Beginner |
Basic FSM, introduces synchronous logic |
|
4 |
|
GPIO & I/O |
π’ Beginner |
Direct pin drive, PMOD pinout awareness |
|
5 |
|
Digital Logic |
π’ Beginner |
Pure combinational, no clock needed |
|
6 |
|
Signal & Timing |
π’ Beginner |
Sequential logic, introduces registers |
|
7 |
|
GPIO & I/O |
π‘ Intermediate |
Sequenced output, simple state machine |
|
8 |
|
GPIO & I/O |
π‘ Intermediate |
FPGA-to-RP2040 IO bridge, bus awareness |
|
9 |
|
GPIO & I/O |
π‘ Intermediate |
FPGA-to-RP2040 IO bridge, wider bus |
|
10 |
|
Communication Protocols |
π‘ Intermediate |
I2C state machine, clock stretching awareness |
|
11 |
|
Communication Protocols |
π‘ Intermediate |
SPI shift register, MISO/MOSI routing |
|
12 |
|
Communication Protocols |
π‘ Intermediate |
UART RX framing, baud clock generation |
|
13 |
|
Communication Protocols |
π‘ Intermediate |
UART input, timing/state machine, serial-to-LED translation |
|
14 |
|
Communication Protocols |
π‘ Intermediate |
UART + datapath, multi-module design |
|
15 |
|
Signal & Timing |
π‘ Intermediate |
PLL primitive instantiation, clock domain |
|
16 |
|
Signal & Timing |
π‘ Intermediate |
Multi-channel counter, duty cycle control |
|
17 |
|
Signal & Timing |
π‘ Intermediate |
BCD conversion, multiplexed display drive |
|
18 |
|
Sensors & Peripherals |
π‘ Intermediate |
Pulse timing, echo measurement FSM |
|
19 |
|
Sensors & Peripherals |
π‘ Intermediate |
Precise bit-bang timing, serial protocol |
|
20 |
|
Signal & Timing |
π΄ Advanced |
RF modulation concepts, carrier + data mixing |
|
21 |
|
Processors & CPUs |
π΄ Advanced |
Custom ISA, stack-based execution, SPI host |
|
22 |
|
Processors & CPUs |
π΄ Advanced |
Full 4-bit SAP CPU: ALU, PC, registers, decode |
|
23 |
|
Processors & CPUs |
π΄ Advanced |
Full 8-bit SAP CPU: wider datapath, more opcodes |
Summary by DifficultyΒΆ
Difficulty |
Count |
Examples |
|---|---|---|
π’ Beginner |
6 |
|
π‘ Intermediate |
13 |
|
π΄ Advanced |
4 |